Two processors, M-5 and M-7, implement the same instruction set. Processor M-5 uses a 5-stage pipeline and a clock cycle of 10 nanoseconds. Processor M-7 uses a 7-stage pipeline and a clock cycle of 7.5 nanoseconds. Which of the following is (are) true? I. M-7�s pipeline has better maximum throughput than M-5�s pipeline. II. The latency of a single instruction is shorter on M-7�s pipeline than on M-5�s pipeline. III. Programs executing on M-7 will always run faster than programs executing on M-5.
(A) I only (B) II only (C) I and III only (D) II and III only (E) I, II, and III
Originally posted by Pat Farrell: (..snip..)I don't see how to answer the other two, it depends on how many stalls you get.
Yep, it's L-2 misses and so on. Great deal of cut and try here. If this is an exam question, then I am not worried about competition from formally trained coders. It's like when I tried to get pissed off at an elephant trainer who pushed around 20,000 pound elphants. He just laughed at me.
"The differential equations that describe dynamic interactions of power generators are similar to that of the gravitational interplay among celestial bodies, which is chaotic in nature."
Originally posted by Pratap Chowdary: yes , it is a exam question
Go to the course's textbook and lookup the definition of "maximum throughput" and "single instruction latency".
1) M-7 process each instruction faster than M-5 (7.5 ms vs 10 ms) 2) Starting from an empty pipeline, M-5 finish processing the first instruction faster (50 ms vs 52.2 ms). From 1) and 2), no processor will be faster than the other always.
Joined: Sep 27, 2006
throughput:the number of instructions that can be executed in a unit of time.
Instruction Latency: time to execute single instruction.
instruction latency in a non-pipelined processor is slightly lower than in a pipelined equivalent.
Joined: Sep 17, 2006
Pentium class will retire about one instruction per clock cycle, consequent to deep branch prediction, speculative execution and instruction retire unit working well on a given stretch. This is one for study, if we can avoid going to ram by keeping a loop on L-2, why would we want to do loop unrolling?
What is an M-5 / M-7 ?
[Pratap Chowdary:] instruction latency in a non-pipelined processor is slightly lower than in a pipelined equivalent
A piplined architecture results in a dramatic speedup,... unless it is number crunching or some such task which can be repetitive, short-loop and reside on the on-chip registers ( gates, memory or whatever - on the circuts in the processor package ) then a non-piplined architecture does not have a clear disadvantage. You would have to have a sophisticated scheduler to get a bank of network traffic in a useable matrix to keep most any processor actually busy ~ in a sense we would think of it.
I’ve looked at a lot of different solutions, and in my humble opinion Aspose is the way to go. Here’s the link: http://aspose.com
subject: tricky question on Processor Instruction pipelining